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ultralogic? 64-macrocell flash cpld cy7c372i cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-03033 rev. *a revised april 16, 2004 features ? 64 macrocells in four logic blocks ? 32 i/o pins ? five dedicated inputs including two clock pins ? in-system reprogrammable (isr?) flash technology ? jtag interface ? bus hold capabilities on all i/os and dedicated inputs ? no hidden delays ?high speed ?f max = 125 mhz ?t pd = 10 ns ?t s = 5.5 ns ?t co = 6.5 ns ? fully pci compliant ? 3.3v or 5.0v i/o operation ? available in 44-pin plcc, tqfp, and clcc packages ? pin-compatible with the cy7c371i functional description the cy7c372i is an in-system reprogrammable complex programmable logic device (cpld) and is part of the f lash 370i? family of high-density, high-speed cplds. like all members of the f lash 370i family, the cy7c372i is designed to bring the ease of use and high performance of the 22v10, as well as pci local bus specification support, to high-density cplds. like all of the ultralogic? f lash 370i devices, the cy7c372i is electrically erasable and isr, which simplifies both design and manufacturing flows, thereby reducing costs. the cypress isr function is implemented through a jtag serial interface. data is shifted in and out through the sdi and sdo pins. the isr interface is enabled using the programming voltage pin (isr en ). additionally, because of the superior routability of the f lash 370i devices, isr often allows users to change existing logic designs while simultaneously fixing pinout assignments. the 64 macrocells in the cy7c372i are divided between four logic blocks. each logic blo ck includes 16 macrocells, a 72 x 86 product term array, and an intelligent product term allocator. the logic blocks in the f lash 370i architecture are connected with an extremely fast and predictable routing resource?the programmable interconnect ma trix (pim). the pim brings flexibility, routability, speed, and a uniform delay to the inter- connect. logic block diagram pim input macrocells clock inputs inputs logic logic 2 2 36 16 16 36 8 i/os 8 i/os 16 16 logic 36 16 16 36 8 i/os 8 i/os 2 3 input/clock macrocells i/o 0 -i/o 7 logic i/o 8 -i/o 15 i/o 16 -i/o 23 i/o 24 -i/o 31 block a block b block d block c
cy7c372i document #: 38-03033 rev. *a page 2 of 13 selection guide 7c372i-125 7c372i-100 7c372i-83 7 c372il-83 7c372i-66 7c372il-66 maximum propagation delay [1] , t pd (ns) 10 12 15 15 20 20 minimum set-up, t s (ns) 5.5 6.0 8 8 10 10 maximum clock to output [1] , t co (ns) 6.5 6.5 8 8 10 10 typical supply current, i cc (ma) 757575457545 pin configurations note: 1. the 3.3v i/o mode timing adder, t 3.3io , must be added to this specification when v ccio = 3.3v. i/o 27 /sdi i/o 26 i/o 25 i/o 24 clk 1 /i 4 gnd i 3 i 2 i/o 23 i/o 22 i/o 21 i/o 5 /sclk i/o 6 i/o 7 i 0 isr en gnd clk 0 /i 1 i/o 8 i/o 9 i/o 10 i/o 11 gnd i/o 20 i/o 2 gnd v ccio v ccint i/o 3 i/o 4 i/o 1 i/o 0 i/o 29 i/o 30 i/o 31 i/o 28 i/o 19 i/o 18 i/o 17 i/o 16 i/o 15 i/o 14 i/o 13 i/o 12 6 53 4 2 8 9 7 10 11 1 44 18 15 16 14 13 12 17 19 20 22 21 23 24 27 26 28 25 31 30 29 32 33 34 39 37 38 36 35 43 42 40 41 plcc topview /smode /sdo 1 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 4443424140 i/o 27 /sdi i/o 26 i/o 25 i/o 24 clk 1 /i 4 gnd i 3 i 2 i/o 23 i/o 22 i/o 21 i/o 5 /sclk i/o 6 i/o 7 i 0 isr en gnd clk 0 /i 1 i/o 8 i/o 9 i/o 10 i/o 11 gnd i/o 20 i/o 2 gnd v cc v cc i/o 3 i/o 4 i/o 1 i/o 0 i/o 29 i/o 30 i/o 31 i/o 28 i/o 19 i/o 18 i/o 17 i/o 16 i/o 15 i/o 14 i/o 13 i/o 12 /smode /sdo clcc topview
cy7c372i document #: 38-03033 rev. *a page 3 of 13 functional description like all members of the f lash 370i family, the cy7c372i is rich in i/o resources. every two macrocells in the device feature an associated i/o pin, resulting in 32 i/o pins on the cy7c372i. in addition, there are three dedicated inputs and two input/clock pins. finally, the cy7c372i features a very simple timing model. unlike other high-density cpld architectures, there are no hidden speed delays such as fanout effects, interconnect delays, or expander delays. regardless of the number of resources used. or the type of application, the timing param- eters on the cy7c372i remain the same. logic block the number of logic blocks distinguishes the members of the f lash 370i family. the cy7c372i includes four logic blocks. each logic block is constructed of a product term array, a product term allocator, and 16 macrocells. product term array the product term array in the f lash 370i logic block includes 36 inputs from the pim and outputs 86 product terms to the product term allocator. the 36 inputs from the pim are available in both positive and negative polarity, making the overall array size 72 x 86. this large array in each logic block allows for very complex functions to be implemented in a single pass through the device. product term allocator the product term allocator is a dynamic, configurable resource that shifts product terms to ma crocells that require them. any number of product terms between 0 and 16 inclusive can be assigned to any of the logic block macrocells (this is called product term steering). furthermore, product terms can be shared among multiple macrocells. this means that product terms that are common to more than one output can be imple- mented in a single product term. product term steering and product term sharing help to increase the effective density of the f lash 370 plds. note that product term allocation is handled by software and is invisible to the user. i/o macrocell half of the macrocells on the cy7c372i have separate i/o pins associated with them. in other words, each i/o pin is shared by two macrocells. the input to the macrocell is the sum of between 0 and 16 product terms from the product term allocator. the macrocell includes a register that can be optionally bypassed. it also has polarity control, and two global clocks to trigger the register. the i/o macrocell also features a separate feedback path to the pim so that the register can be buried if the i/o pin is used as an input. buried macrocell the buried macrocell is very similar to the i/o macrocell. again, it includes a register that can be configured as combi- natorial, as a d flip-flop, a t flip -flop, or a latch. the clock for this register has the same options as described for the i/o macrocell. one difference on the buried macrocell is the addition of input register capa bility. the user can program the buried macrocell to act as an i nput register (d-type or latch) whose input comes from the i/o pin associated with the neigh- boring macrocell. the output of all buried macrocells is sent directly to the pim regard less of its configuration. programmable interconnect matrix the programmable interconnect matrix (pim) connects the four logic blocks on the cy7c3 72i to the inputs and to each other. all inputs (including feedbacks) travel through the pim. there is no speed penalty incurred by signals traversing the pim. programming for an overview of isr programming, refer to the f lash 370i family data sheet and for isr cable and software specifica- tions, refer to isr data sheets. for a detailed description of isr capabilities, refer to t he cypress application note, ?an introduction to in system reprogramming with f lash 370i.? pci compliance the f lash 370i family of cmos cplds are fully compliant with the pci local bus specification published by the pci special interest group. the simple and predictable timing model of f lash 370i ensures compliance with the pci ac specifications independent of the design. on the other hand, in cpld and fpga architectures without simple and predictable timing, pci compliance is dependent upon routing and product term distri- bution. 3.3v or 5.0v i/o operation the f lash 370i family can be configured to operate in both 3.3v and 5.0v systems. all devices have two sets of v cc pins: one set, v ccint , for internal operation and input buffers, and another set, v ccio , for i/o output drivers. v ccint pins must always be connected to a 5.0v power supply. however, the v ccio pins may be connected to either a 3.3v or 5.0v power supply, depending on the output requirements. when v ccio pins are connected to a 5.0v so urce, the i/o voltage levels are compatible with 5.0v systems. when v ccio pins are connected to a 3.3v source, the input voltage levels are compatible with both 5.0v and 3.3v systems, while the output voltage levels are compatible with 3.3v systems. there will be an additional timing delay on all output buffers when operating in 3.3v i/o mode. the added flex ibility of 3.3v i/o capability is available in commercial and industrial temperature ranges. bus hold capabilities on all i/os and dedicated inputs in addition to isr capability, a new feature called bus-hold has been added to all f lash 370i i/os and dedicated input pins. bus-hold, which is an improved version of the popular internal pull-up resistor, is a weak latch connected to the pin that does not degrade the device?s performance. as a latch, bus-hold recalls the last state of a pin when it is three-stated, thus reducing system noise in bus-in terface applications. bus-hold additionally allows unused device pins to remain unconnected on the board, which is particular ly useful during prototyping as designers can route new signals to the device without cutting trace connections to v cc or gnd. design tools development software for the cy7c372i is available from cypress?s warp ?, warp professional?, and warp enter- prise? software packages. please refer to the data sheets on these products for more details. cypress also actively supports almost all third-party design tools. please refer to third-party tool support for further information.
cy7c372i document #: 38-03033 rev. *a page 4 of 13 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage to ground potential ............... ?0.5v to +7.0v dc voltage applied to outputs in high-z state ............................................... ?0.5v to +7.0v dc input voltage............................................ ?0.5v to +7.0v dc program voltage .....................................................12.5v output current into outputs ........................................ 16 ma static discharge voltage......... .............. .............. ...... > 2001v (per mil?std?883, method 3015) latch-up current..................................................... > 200 ma operating range range ambient temperature v cc v ccint v ccio commercial 0 c to +70 c5v 0.25v 5v 0.25v or 3.3v 0.3v industrial ? 40 c to +85 c5v 0.5v 5v 0.5v 3.3v 0.3v military [2] ?55c to +125c 5v 0.5v electrical characteristics over the operating range [3, 4] parameter description test conditions min. typ. max. unit v oh output high voltage v cc = min. i oh = ?3.2 ma (com?l/ind) [5] 2.4 v i oh = ?2.0 ma (mil) 2.4 v v ohz output high voltage with output disabled [8] v cc = max. i oh = 0 a (com?l/ind) [5, 6] 4.0 v i oh = ?50 a (com?l/ind) [5, 6] 3.6 v v ol output low voltage v cc = min. i ol = 16 ma (com?l/ind) [5] 0.5 v i ol = 12 ma (mil) 0.5 v v ih input high voltage guaranteed input logical high voltage for all inputs [7] 2.0 7.0 v v il input low voltage guaranteed input logical low voltage for all inputs [7] ?0.5 0.8 v i ix input load current v i = internal gnd, v i = v cc ?10 +10 a i oz output leakage current v cc = max., v o = gnd or v o = v cc , output disabled ?50 +50 a v cc = max., v o = 3.3v, output disabled [6] 0 ?70 ?125 a i os output short circuit current [8, 9] v cc = max., v out = 0.5v ?30 ?160 ma i cc power supply current [10] v cc = max., i out = 0 ma, f = 1 mhz, v in = gnd, v cc com?l/ind. 75 125 ma com?l ?l? ?66 45 75 ma military 75 200 ma i bhl input bus hold low sustaining current v cc = min., v il = 0.8v +75 a i bhh input bus hold high sustaining current v cc = min., v ih = 2.0v ?75 a i bhlo input bus hold low overdrive current v cc = max. +500 a i bhho input bus hold high overdrive current v cc = max. ? 500 a notes: 2. t a is the ?instant on? case temperature. 3. see the last page of this specification for group a subgroup testing information. 4. if v ccio is not specified, the device can be operating in either 3.3v or 5v i/o mode; v cc = v ccint . 5. for sdo: i oh =?2 ma, i ol = 2 ma. 6. when the i/o is three-stated, the bus-hold circuit can weakly pull the i/o to a maximum of 4.0v if no leakage current is allo wed. this voltage is lowered significantly by a small leakage current. note that all i/os are three-stated during isr programming. refer to the application note ?understa nding bus hold? for additional information. 7. these are absolute values with respect to device ground. a ll overshoots due to system or tester noise are included. 8. not more than one output should be tested at a time. duration of the short circuit should not exceed 1 second. v out = 0.5v has been chosen to avoid test problems caused by test er ground degradation. 9. tested initially and after any design or process changes that may affect these parameters. 10. measured with 16-bit counter programmed into each logic block.
cy7c372i document #: 38-03033 rev. *a page 5 of 13 note: 11. c i/o for dedicated inputs, and for i/o pins with jtag functionality is 12 pf max., and for isr en is 15 pf max. 12. c i/o for clcc package is 15 pf max. 13. t er measured with 5-pf ac test load and t ea measured with 35-pf ac test load. capacitance [9] parameter description test conditions min. max. unit c i/o [11, 12] input capacitance v in = 5.0v at f = 1 mhz 8 pf c clk clock signal capacitance v in = 5.0v at f = 1 mhz 5 12 pf inductance [9] parameter description test conditions 44-lead clcc 44-lead plcc unit l maximum pin inductance v in = 5.0v at f = 1 mhz 2 5 nh endurance characteristics [9] parameter description test conditions max. unit n maximum reprogramming cycles normal programming conditions 100 cycles ac test loads and waveforms parameter [13] v x output waveform measurement level t er(?) 1.5v t er(+) 2.6v t ea(+) 1.5v t ea(?) v the (d) test waveforms 90% 10% 3.0v gnd 90% 10% all input pulses 5v output 35 pf including jig and scope 5v output 5 pf including jig and scope (a) (b) <2ns <2 ns output 238 ? (com'l) 319 ? (mil) 170 ? (com'l) 236 ? (mil) 99 ? (com'l) 136 ? (mil) equivalent to: th venin equivalent 2.08v(com'l) 2.13v(mil) 238 ? (com'l) 319 ? (mil) 170 ? (com'l) 236 ? (mil) (c) v oh 0.5v v x 0.5v v ol v x 0.5v v x v oh 0.5v v x v ol
cy7c372i document #: 38-03033 rev. *a page 6 of 13 switching characteristics over the operating range [14] parameter description 7c372i-125 7c372i-100 7c372i-83 7c372il-83 7c372i-66 7c372il-66 unit min. max. min. max. min. max. min. max. combinatorial mode parameters t pd input to combinatorial output [1] 10 12 15 20 ns t pdl input to output through transparent input or output latch [1] 13 15 18 22 ns t pdll input to output through transparent input and output latches [1] 15 16 19 24 ns t ea input to output enable [1] 14 16 19 24 ns t er input to output disable 14 16 19 24 ns input registered/latched mode parameters t wl clock or latch enable input low time [9] 3345ns t wh clock or latch enable input high time [9] 3345ns t is input register or latch set-up time 2 2 3 4 ns t ih input register or latch hold time 2 2 3 4 ns t ico input register clock or latch enable to combinatorial output [1] 14 16 19 24 ns t icol input register clock or latch enable to output through transparent output latch [1] 16 18 21 26 ns output registered/latched mode parameters t co clock or latch enable to output [1] 6.5 6.5 8 10 ns t s set-up time from input to clock or latch enable 5.5 6 8 10 ns t h register or latch data hold time 0 0 0 0 ns t co2 output clock or latch enable to output delay (through memory array) [1] 14 16 19 24 ns t scs output clock or latch enable to output clock or latch enable (through memory array) 8101215ns t sl set-up time from input through transparent latch to output register clock or latch enable 10 12 15 20 ns t hl hold time for input through transparent latch from output register clock or latch enable 0000ns f max1 maximum frequency with internal feedback in output registered mode (least of 1/t scs , 1/(t s + t h ), or 1/t co ) [9] 125 100 83 66 mhz f max2 maximum frequency data path in output registered/latched mode (lesser of 1/(t wl + t wh ), 1/(t s + t h ), or 1/t co ) [9] 153.8 153.8 125 100 mhz f max3 maximum frequency with external feedback (lesser of 1/(t co + t s ) and 1/(t wl + t wh )) [9] 83.3 80 62.5 50 mhz t oh -t ih 37x output data stable from output clock minus input register hold time for 7c37x [9, 15] 0000ns pipelined mode parameters t ics input register clock to out put register clock 8 10 12 15 ns f max4 maximum frequency in pipelined mode (least of 1/(t co + t is ), 1/t ics , 1/(t wl + t wh ), 1/(t is + t ih ), or 1/t scs ) [9] 125 100 83.3 66.6 mhz notes: 14. all ac parameters are measured with 16 outputs switching and 35-pf ac test load. 15. this specification is intended to guarantee interface co mpatibility of the other members of the cy7c370i family with the cy7 c372i. this specification is met for the devices operating at the same ambient temperature and at the same power supply voltage.
cy7c372i document #: 38-03033 rev. *a page 7 of 13 reset/preset parameters t rw asynchronous reset width [9] 10 12 15 20 ns t rr asynchronous reset recovery time [9] 12 14 17 22 ns t ro asynchronous reset to output [1] 16 18 21 26 ns t pw asynchronous preset width [9] 10 12 15 20 ns t pr asynchronous preset recovery time [9] 12 14 17 22 ns t po asynchronous preset to output [1] 16 18 21 26 ns tap controller parameter f tap tap controller frequency 500 500 500 500 khz 3.3v i/o mode parameters t 3.3io 3.3v i/o mode timing adder 1 1 1 1 ns switching waveforms switching characteristics over the operatin g range (continued) [14] parameter description 7c372i-125 7c372i-100 7c372i-83 7c372il-83 7c372i-66 7c372il-66 unit min. max. min. max. min. max. min. max. t pd input combinatorial output combinatorial output registered output t s input clock t co registered output t h clock t wl t wh
cy7c372i document #: 38-03033 rev. *a page 8 of 13 switching waveforms (continued) latched output t s input latch enable t co latched output t h t pdl registered input t is registered input input register clock t ico combinatorial output t ih clock t wl t wh clock to clock registered input input register clock t ics output register clock t scs
cy7c372i document #: 38-03033 rev. *a page 9 of 13 switching waveforms (continued) latched input and output t ics latched input output latch enable latched output t pdll latch enable t wl t wh t icol input latch enable t sl t hl asynchronous reset input t ro registered output clock t rr t rw asynchronous preset input t po registered output clock t pr t pw
cy7c372i document #: 38-03033 rev. *a page 10 of 13 ordering information speed (mhz) ordering code package name package type operating range 125 cy7c372i-125jc j67 44-lead plastic leaded chip carrier commercial 100 cy7c372i-100jc j67 44-lead plastic leaded chip carrier commercial cy7c372i-100ji j67 44-lead plastic leaded chip carrier industrial 83 cy7c372i-83jc j67 44-lead plastic leaded chip carrier commercial cy7c372i-83ji j67 44-lead plastic leaded chip carrier industrial cy7c372i-83ymb y67 44-lead ceramic leaded chip carrier military 83 cy7c372il-83jc j67 44-lead plastic leaded chip carrier commercial 66 cy7c372i-66jc j67 44-lead plastic leaded chip carrier commercial cy7c372i-66ji j67 44-lead plastic leaded chip carrier industrial CY7C372I-66YMB y67 44-lead ceramic leaded chip carrier military 66 cy7c372il-66jc j67 44-lead plastic leaded chip carrier commercial switching waveforms (continued) input t er outputs t ea output enable/disable
cy7c372i document #: 38-03033 rev. *a page 11 of 13 military specifications group a subgroup testing dc characteristics parameter subgroups v oh 1, 2, 3 v ol 1, 2, 3 v ih 1, 2, 3 v il 1, 2, 3 i ix 1, 2, 3 i oz 1, 2, 3 i cc 1, 2, 3 switching characteristics parameter subgroups t pd 9, 10, 11 t co 9, 10, 11 t ico 9, 10, 11 t s 9, 10, 11 t h 9, 10, 11 t is 9, 10, 11 t ih 9, 10, 11 t ics 9, 10, 11 package diagrams 44-lead plastic leaded chip carrier j67 51-85003-*a
cy7c372i document #: 38-03033 rev. *a page 12 of 13 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. isr, ultralogic, f lash 370, f lash 370i, warp , warp professional, and warp enterprise, are trademarks of cypress semiconductor corporation. package diagrams (continued) 44-pin ceramic leaded chip carrier y67 51-80014-**
cy7c372i document #: 38-03033 rev. *a page 13 of 13 document history page document title: cy7c372i ultr alogic? 64-macrocell flash cpld document number: 38-03033 rev. ecn no. issue date orig. of change decsription of change ** 106378 06/18/01 szv change from spec# 38-00498 to 38-03033 *a 213375 see ecn fsg added note to title page: ?use ultra37000 for all new designs?

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